The present invention relates, in general, to a programmable logic device (PLD) and, more particularly, to a combination address buffer/multiplexer/driver implemented in a programmable logic device.
Present techniques for multiplexing addresses to a memory device, such as a dynamic random access memory (DRAM) or the like, consists of two levels of logic. In the first level, an address is latched into a buffer. In the second level, the address is multiplexed prior to being provided to the memory. This implementation results in two levels of delays and requires that separate board real estate space be provided for both circuits.
Therefore, a need exists for a faster means of processing the address signals in an implementation which will require less board space.
Accordingly, it is an object of the present invention to provide an address buffer, multiplexer, and driver which is implemented in one level of logic thereby eliminating one of the levels of delay.
It is another object of the present invention to provide an address buffer, multiplexer, and driver which is implemented in a single device requiring less board space.